The present invention relates generally to DC-DC power converters and, more particularly, to DC-DC power converters that automatically switch between continuous-conduction mode (CCM) and discontinuous-conduction mode (DCM).
FIG. 1 is a schematic block diagram of a conventional DC-DC buck power converter 100 that converts a DC input voltage DCDC_IN into a lower DC output voltage DCDC_OUT. In general, the DC-DC converter 100 has control circuitry (110, 120, and 130, described below) that generates control signals PCTRL and NCTRL that are respectively applied to the gates of a p-type MOS transistor switch P_SW and an n-type MOS transistor switch N_SW. When the control signals PCTRL and NCTRL are both low, the switch P_SW is on and the switch N_SW is off, such that the internal node LP is connected to DCDC_IN. When the control signals PCTRL and NCTRL are both high, the switch P_SW is off and the switch N_SW is on, such that the internal node LP is connected to ground. When the control signal PCTRL is high and the control signal NCTRL is low, both switches P_SW and N_SW are off, such that the internal node LP is isolated from both DCDC_IN and ground. The control circuitry is designed such that the control signal PCTRL is never low when the control signal NCTRL is high, so the switches P_SW and N_SW are never both on at the same time.
The DC-DC converter 100 can be operated in either a continuous-conduction mode (CCM) or a discontinuous-conduction mode (DCM). In the CCM mode, the control circuitry controls the switches P_SW and N_SW such that current continuously flows through the inductor L. In certain circumstances, during the CCM mode, the inductor current continuously cycles between positive currents (i.e., current flowing from the internal node LP to the output node DCDC_OUT) and negative currents (i.e., current flowing from the output node DCDC_OUT to the internal node LP). In the DCM mode, the control circuitry controls the switches P_SW and N_SW such that (ideally) the current flowing through the inductor L is never negative. In certain circumstances, during the DCM mode, the inductor current is discontinuous. During cycles in which the inductor current always remains positive, there is no substantive difference between the CCM mode and the DCM mode.
FIG. 2 is a signal diagram illustrating the current flowing through the inductor L during one possible scenario involving an ideal CCM mode (left side of FIG. 2) followed by an ideal DCM mode (right side of FIG. 2) for the DC-DC converter 100. During the CCM mode, the current flowing through the inductor L continuously and linearly cycles between a maximum positive current level and a maximum negative current level. During the DCM mode, the inductor current intermittently cycles linearly between zero current and a maximum positive current level.
In general, during both the CCM mode and the DCM mode, the inductor current is increased by turning on the switch P_SW and turning off the switch N_SW to connect the internal node LP to the input node DCDC_IN, and the inductor current is decreased by turning off the switch P_SW and turning on the switch N_SW to connect the internal node LP to ground. By turning off both switches P_SW and N_SW when the inductor current reaches zero, the inductor current can be kept at zero during the time periods between the intermittent positive-current cycles of the DCM mode.
During the CCM mode, when the inductor current is to be decreased, the switch P_SW is kept off and the switch N_SW is kept on long enough for the inductor current to decrease to the maximum negative current level. During the DCM mode, however, when the inductor current is to be decreased, the switch P_SW is kept off and the switch N_SW is kept on only long enough for the inductor current to decrease to zero. When the inductor current reaches zero, the control circuitry turns off the switch N_SW, while keeping the switch P_SW off. In that case, the inductor current will remain at zero until the control circuitry determines that the inductor current needs to be increased again for the next DCM positive-current cycle, at which time, the control circuitry will turn on the switch P_SW, while keeping the switch N_SW off.
Referring again to FIG. 1, the control circuitry for the DC-DC converter 100 includes all of the elements shown in FIG. 1 except for the switches P_SW and N_SW and the inductor L. The function of the control circuitry is to generate the switch control signals PCTRL and NCTRL that control the turning on and turning off of the switches P_SW and N_SW, respectively. The control circuitry includes a main control loop 110, zero-crossing detection (ZCD) circuitry 120, and an AND gate 130.
The main control loop 110 includes a feedback controller 111, a pulse-width modulator (PWM) 112, and a pre-driver 113. During both the CCM mode and the DCM mode and based on the voltage feedback signal dcdc_out_sns_1, the main control loop 110 generates the switch control signal PCTRL that is applied to the gate of the switch P_SW and the main-loop control signal 114 that is applied to one of the inputs to the AND gate 130.
The ZCD circuitry 120 includes a ZCD comparator 121, a ZCD flip-flop 123, an inverting ZCD set-reset (SR) latch 124, and inverters 125 and 127. During the DCM mode and based on the voltage at the internal node LP, the ZCD circuitry 120 generates the latch output signal zcd_b_latch that is applied to the other input to the AND gate 130. The purpose of the ZCD circuitry 120 is to detect when the inductor current reaches zero during the DCM mode in order to determine when to turn off the switch N_SW.
The AND gate 130 receives both the main-loop control signal 114 and the latch output signal zcd_b_latch and generates the control signal NCTRL.
During the CCM mode, the ZCD comparator 121 is disabled such that the latch output signal zcd_b_latch is always high. (Note that the control signal for disabling/enabling the ZCD comparator 121 is not shown in FIG. 1.) When the latch output signal zcd_b_latch is high, the AND gate 130 ensures that the switch control signal NCTRL is equal to the main-loop control signal 114. Thus, when the ZCD comparator 121 is disabled during the CCM mode, the main control loop 110 generates the switch control signals PCTRL and NCTRL to cause the inductor current to go both positive and negative.
During the CCM mode, the ZCD comparator 121 is enabled to configure the DC-DC converter 100 into the DCM mode. The ZCD comparator 121 compares the voltage at the internal node LP to the ground voltage GND. The resulting ZCD comparator output 122 is applied to the clock input CK of the ZCD flip-flop 123, which also receives (i) the input signal TIE_HIGH at its data input D and (ii) the reset signal reset_zcd at its reset input R.
Although not shown in FIG. 1, the DC-DC converter 100 has circuitry that generates the signal TIE_HIGH to be equal to the input voltage DCDC_IN. The flip-flop reset signal reset_zcd is generated by the inverter 125 to be the complement of the switch control signal NCTRL. The latch input signal zcd_latch, which is generated at the data output Q of the ZCD flip-flop 123, is applied as input to the inverting ZCD SR latch 124, which in turn generates the latch output signal zcd_b_latch as the complement to the latch input signal zcd_latch. Note that the ZCD SR latch 124 also receives a latch reset signal 128, which is generated by the inverter 127 to be the complement of the switch control signal PCTRL.
During the DCM mode, when the inductor current is to be increased (i.e., from 0 to the maximum positive current), the control circuitry causes the control signals PCTRL and a main-loop control signal 114 output from the pre-driver 113 to be both low, such that the switch control signals PCTRL and NCTRL are both low to turn on the switch P_SW and turn off the switch N_SW. In that case, the voltage at the internal node LP will be less than the ground voltage GND, the comparator output signal 122 will remain low, and the ZCD flip-flop 123 will not be triggered. With the switch control signal NCTRL low, the flip-flop reset signal reset_zcd will be high, which will reset the ZCD flip-flop 123, causing the latch input signal zcd_latch to be low. With the switch control signal PCTRL also low, the latch reset signal 128 will be high. In that case, the latch output signal zcd_b_latch will be high, and the switch control signal NCTRL will be determined by the low main-loop control signal 114 from the pre-driver 113.
During the DCM mode, after the inductor reaches the maximum positive current, the inductor current is to be decreased to 0. As such, the control circuitry causes the control signals PCTRL and the main-loop control signal 114 to be both high, such that the switch control signals PCTRL and NCTRL are both high to turn off the switch P13 SW and turn on the switch N_SW. Note that the latch output signal zcd_b_latch is still initially high. In that case, as the positive inductor current decreases, the voltage at the internal node LP increases.
When the voltage at the internal node LP crosses zero and become positive, the ZCD comparator output signal 122 will be driven from low to high, thereby triggering the ZCD flip-flop 123. With the switch control signal NCTRL high, the flip-flop reset signal reset_zcd will be low, thereby allowing the latch input signal zcd_latch to be driven high based on the high flip-flop input signal TIE_HIGH. With the switch control signal PCTRL also high, the latch reset signal 128 will be low. In that case, the latch output signal zcd_b_latch will be low, and the switch control signal NCTRL will be driven low, thereby turning off the switch N_SW (even though the main-loop control signal 114 is still high).
Note that the main control loop 110 will continue to periodically generate high values for the main-loop control signal 114, but, since the latch output signal zcd_b_latch will remain low, the switch control signal NCTRL will also remain low, thereby keeping the switch N_SW off. In this way, the inductor current is prevented or at least inhibited from being driven negative during the DCM mode. As a result, the inductor current will remain at zero until the control circuitry determines that it is again time to start another DCM cycle of positive inductor current by driving both the switch control signal PCTRL and the main-loop control signal 114 low to turn on the switch P_SW, while keeping the switch N_SW off.
In order to achieve stable operations efficiently, at start-up, the DC-DC converter 100 is initially configured in the CCM mode with the ZCD comparator 121 disabled. If and when the control circuitry determines that operations should be in the DCM mode, the control circuitry will enable the ZCD comparator 121 to transition from the CCM mode to the DCM mode. Unfortunately, during such transitions, because the main control loop 110 cannot quickly adjust its duty cycle from the relatively large duty cycle of the CCM mode to the relatively small duty cycle of the DCM mode, the output voltage DCDC_OUT can become undesirably high, which can potentially damage the downstream circuitry (not shown) powered by the output voltage DCDC_OUT.
In addition, when the DC-DC converter 100 is operated in the DCM mode, if the output current loading decreases suddenly and significantly, the output voltage DCDC_OUT can also become undesirably high, because, here, too, the main control loop 110 cannot adjust its duty cycle quickly enough from the relatively large duty cycle of the DCM mode with relatively high output current loading to the relatively small duty cycle of the DCM mode with relatively low output current loading.